High-speed Transceiver Design in Cmos Using Multi-level (4-pam) Signaling
نویسنده
چکیده
JOSEPH, BALU High-Speed Transceiver Design in CMOS using Multilevel (4-PAM) Signaling. (Under the direction of Dr. Wentai Liu) The design of a 4 Gbps serial link transceiver in 0.35μm CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty and on-chip frequency limitations. The design uses a combination of multi-level signaling (4-PAM) and transmit pre-emphasis to overcome the channel low-pass characteristics. High on-chip frequency signals are avoided by multiplexing and de-multiplexing the data directly at the pads. Timing recovery is done through over-sampling the data using multi-phase clocks generated from a low-jitter PLL. The design achieves a 4 Gbps data transmission rate, with a transmit data jitter of 53.2 ps (p-p), while consuming 879.4 mW of power from a 3.3 V supply. HIGH-SPEED TRANSCEIVER DESIGN IN CMOS USING MULTI-LEVEL (4-PAM) SIGNALING
منابع مشابه
A CMOS 4-PAM Multi-Gbps Serial Link Transceiver A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE OF GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
As the demand for higher data-rate communication increases, low-cost, high-speed serial links using copper cables become attractive for distances of 1 to 10 meters. For multi-Gbps applications, the data rate is limited by the channel low-pass characteristics due to cable skin-effect loss and the speed of the process technology. This design uses a receiver equalizer in combination with a transmi...
متن کاملA novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception
-Transmission of signals, whether on-chip or off-chip, places severe constraints on timing and extracts a large price in energy. New silicon device technologies, such as backplane CMOS, provide a programmable and adaptable threshold voltage as an additional tool that can be used for low power design. We show that one particularly desirable use of this freedom is energy-efficient high-speed tran...
متن کاملAn Adaptive PAM-4 5-Gb/s Backplane Transceiver in 0.25- m CMOS
This paper describes a backplane transceiver, which uses pulse amplitude modulated four-level (PAM-4) signaling and continuously adaptive transmit-based equalization to move 2.5-GBd/s symbols totalling 5 Gb/s across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The 17-mm device is implemented in a 0.25m CMOS process, operates off of 2.5...
متن کاملData Converters for High Speed CMOS Links A PhD Thesis
The long links that interconnect networking and computing systems and boards need high throughput to avoid expensive, massively parallel connections. However, long wires suffer signal losses that increase with frequency. Digital communication techniques can compensate for these losses, but require Analog-to-Digital and Digital-to-Analog converters (ADCs and DACs). To understand the application ...
متن کاملPAM-4 Signaling over VCSELs with 0.13μm CMOS Chip Technology
We present results for VCSEL based links operating PAM-4 signaling using a commercial 0.13μm CMOS technology. We perform a complete link analysis of the Bit Error Rate, Q factor, random and deterministic jitter by measuring waterfall curves versus margins in time and amplitude. We demonstrate that VCSEL based PAM–4 can match or even improve performance over binary signaling under conditions of ...
متن کامل